Logic performing device



May 18, 1965 L. HELLERMAN 3,184,603

LOGIC PERFORMING DEVICE Filed Feb. 23, 1961 2 Sheets-Sheet 1 FIGJ F I CE 2 n FIG. 20 24 53 1/H 561 0 L M2 M3? OR F1630 0 24 /58 3 0 0 I M22 4 142 52 0 4 4" l 1 1 56 INVENTOR LEO HELLERMAN g m C d ATTORNE Y @May 18,1965 HELLERMAN LOGIC PERFORMING DEVICE 2 Sheets-Sheet 2 F|G.4o"EXCLUSIVE 0R" Filed Feb. 25, 1961 Lyn FIG. 5b FIG. 5

"EXCLUSIVE 0R FIG.50

United States Patent bull 3,184,603 LOGEC PERFORMXNG DEVEQE LeoHellerman, Pong heepsie, N.Y., assignor to Internationai BusinessMachines Qcrporation, New York, N.Y., a corporation of New York FiledFeb. 23, 196i, Ser. No. 91;)88 it? tllaims. (Cl. 30788.5)

This invention relates to logic circuits and more particularly to logiccircuits adapted to perform all logic functions including, for example,the AND, OR and Exclusive OR functions.

Digital computers and data handlin equipment process information bymeans of electrical signals representing digital values. Circuits areemployed in such equipment to control the path of the electrical signalsor to generate a signal in accordance with the occurrence andconcurrence of signal conditions established within the circuit.Combinations of such circuits can perform computations or manipulationsin accordance with a logic system. Ac-

cordingly, such circuits are known as logic circuits.

Large digital computers can perform a wide variety of manipulations andcomputations. To do this, a multitude of logic circuits are required inthe computers for the particular manipulations and computations.Conventionally, each logic circuit is arranged on a supporting member,typically a printed circuit, and occupies space in the computer. As theflexibility and versatility of the computer increases, the volume of thecomputer grows proportionally. It is desirable, therefore, that thevolume of the computer be reduced to the minimum consonant with themanipulations and computations performed by the computer.

Obviously, one method of decreasing the size of the computer is toreduce the number of logic circuits. Logic circuits adapted to provide avariety of logic functions or universal logic circuits serve this end.Universal logic circuits may exist in several forms.

in one case, a single current is supplied to the circuit and binarysignals control the circuit to obtain the desired output. An example ofa logic circuit that operates in this manner is shown in U.S. Patent2,952,792 to E. F. Yhap, issued September 13, 1960, and assigned to thesame assignee as that of the present invention. In another case, one oftwo binary input signals is available to the circuit and binary signalscontrol the output of the circuit. The present invention is directed toa universal logic circuit of this type. Such universal logic circuitsshould be easily converted from one logic function to another, suitablefor use with various computers and economical in cost.

A general object of the present invention is an improved universal logiccircuit which controls binary input signals as contrasted with a singleinput current.

One object is a sturdy, easily fabricated logic package that is readilyaltered to perform different logic functions.

Another object is a universal logic package that can be suitablyinterconnected to perform binary logic for any finite number ofindependent variables.

These and other objects are accomplished in the present invention, oneillustrative embodiment of which comprises a supporting member having atleast two sets of conductive paths thereon. One conductive path of a setis connected to the corresponding conductive path of the other setthrough an associated interconductive path. A plurality of pairs ofswitching devices are arranged on the supporting member and cooperatewith the conductive paths. One switching device in each pair isconnected to a selected one of the conductive paths in a set. The otherswitching device in a set is connected to the associated interconductivepath of the set. A source of binary control signals is connected to theswitching device.

2,832,897 to D. A. Buck issued April 29, 1958.

"ice

Means are provided for shunting one switching device in each pair ofswitching devices to arrange the circuit for a selected logic operation.Completing the invention is means for supplying at least one of twobinary input signals to the unshunted switching devices which inresponse to a binary control signal, perform the logic operationestablished by shunting selected switching devices.

One feature of the present invention is a unique circuit configurationarranged on a supporting member, typically a glass substrate or thelike, the circuit including pairs of switching points which may beselectively operated to perform a desired logic operation in response toone of two possible input signals supplied to the circuit.

Another feature is a selection circuit which controls the switchnigdevices of a universal logic circuit, the selection circuit arrangingthe switching device to perform a selected logic operation.

Still another feature is a plurality of universal binary logic circuitsand circuit means for selecting one of the binary logic circuits so thatany finite number of independent binary variables can be combined in aselected logic operation.

A specific feature is a circuit configuration having a plurality ofswitching or control points, each control point including a pair ofswitching devices, one of said devices at every control point beingbypassed to enable the resulting combination of bypassed switchingdevices to perform a desired logic operation in response to appropriatebinary signals.

Another specific feature is a universal logic circuit employingsuperconductive paths on a supporting member and pairs of cryotrons forcontrolling the currents along the superconductive paths in accordancewith a logical function when one of two binary input signals and one oftwo binary control signals are supplied to the circuit and selectedcryotrons are bypassed from the circuit.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of preferred embodiments of the invention, as illustrated inthe accompanying drawings wherein:

FIG. 1 is an electrical schematic of one embodiment of the novelcircuitry of the present invention;

FIG. 2 is the circuit of FIG. 1 arranged as an AND circuit;

FIG. 2a is a tabulation of inputs and outputs for the circuit of FIG. 2;

FIG. 3 is the circuit of FIG. 1 arranged as an ()R" circuit;

FIG. 3a is a tabulation of inputs and outputs for the circuit of FIG. 3;

FIG. 4 is the circuit of FIG. 1 arranged as an EX- clusive OR circuit;

PEG. 4a is a tabulation of inputs and outputs for the circuit of FIG. 4;

FIG. 5 is an electrical schematic of the novel circuitry of the presentinvention for handling three independent variables; and FIGS. 5a, b andc are tabulations of inputs and outputs for AND, OR and Exclusive ORcircuits respectively of the type shown in FIG. 5.

One illustrative embodiment of the present invention has application incryogenic systems which are Well known in the art being described, forexample, in US. Patent The cryogenic embodiment is shown in FiG. 1wherein a plurality of thin film cryotrons 2t}, 22-, 30, 32, 4th, 42,St) and 52 are built up on a supporting member, typically a glasssubstrate in the manner disclosed in US. application, Serial No.625,512, filed November 30, 1956 by R. L. Garyin and assigned to thesame assignee as that of the present invention. The glass substrate andcryotrons form a sturdy member for the present invention and may bereadily manufactured at low cost by means of mass production techniques.All of the cryotrons on the glass substrate include a gate conductor 33and a control conductor 35 as is well understood in the cryotron art.Since the previously mentioned cryotrons will be selectively connectedtogether to perform various logic functions, they will be hereinafterreferred to as logic cryotrons.

The control conductors of the logic cryotrons 20, 22, 40 and 42 areconnected in series to form a superconductive path or lead 38.Similarly, the control conductors of the logic cryotrons 30, 32, 50 and52 are connected in series to form a superconductive path or lead 41,the former being connected to a source 39 of binary signals indicativeof a binary whereas the latter are connected to a signal source 43indicative of a binary 1.

The gate conductors of the cryotrons 20 and 3t) are'connected in seriesto form a superconductive path or lead 24 which connects to a signalsource 44 indicative of a binary 0. Similarly, the gate conductor of thecryotrons 22 and 32 are also connected in series to form asuperconductive path 26 which is connected to the path 24 at a node 48.The path 26 is also connected to a superconductive path 28 at a node 56which will be described hereinafter.

In contrast, the gate conductors of the cryotrons 40, 42, t and 52 areconnected to a source 49 of binary signals indicative of a binary l, thegate conductors of the cyrotrons 40 and 50 being connected in series toform the superconductive path 28 whereas the gate conductors of thecryotrons 42 and 52 are connected in series to form a superconductivepath 53. The latter path is connected to the path 28 at a node 54. Also,the path 53 is connected to the path 24 at a node 58 to complete the universal logic block. Output signals from the block appear at the lines 57and 59, binary 0 signals appearing on line 59 leaving the node 58whereas binary 1 signals appear on line 57 leaving the node 56.

Both the binary 1 signal sources 43 and 49 and the binary 0 signalsources 39 and 44 employ a positive current to indicate the presence ofthe particular signal. The signal sources 44 and 49 will hereinafter bereferred to as binary input signals whereas the signal sources 39 and 43will be hereinafter be referred to as binary control signals. Normally,all signal sources are disconnected from the universal logic circuit.During operation of the computer, however, the signal sources areselectively connected to the universal logic circuit in accordance withtechniques well known in the computer art, the logic circuit receivingone of the two binary input signals and employing one of the two binarycontrolling signals to combine the signals according to a preselectedlogic operation.

Also included in the supporting member are control cryotrons 22, 32,40', 42', 50 and 52', each of the previously mentioned cryotrons beingassociated with the logic cryotron having the corresponding unprimedreference designation. Gate conductors 36' of the control cryotrons areconnected in parallel with the gate conductors of the logic cryotronsassociated therewith. Control conductors of the control cryotron 20',22', 24' and 26' are individually connected to different contacts of aselection switch 60, typically a rotary switch having selector arms 62and 63. The arm 62 is limited to supplying current from a source 64through contacts 71 and '72 to the control cryotrons and 42. Similarly,the arm 63 is limited to supplying current from the source 64 throughcontacts 73 and 74 to the control cryotrons 20' and 22'. Controlconductors 35' of the control cryotrons 30, 32', and 52 are alsoindividually connected to different contacts of a selector switch 65having selector arms 66 and 67 connected to a current source 70. Thearms 66 and 67 are limited to supplying current to the control cryotrons30' and 32' and 50' and 52, respectively through contacts 75 and 76 and77 and 78, respectively.

Normally, the inductance of the path, associated with the controlcrytron is of a lesser magnitude than the inductance of the path throughthe logic cryotron associated therewith. Consequently, when both thecontrol and the logic cryotrons are superconductive, current applied tothe lines 24 and 28 normally flows to the control cryotrons. Thesephenomena are in accordance with well known cryogenic principles asdescribed for example in US. patent application Serial No. 77,777, filedDecember 22, 1960, and assigned to the same assignee as that of thepresent invention. When either the logic or control cryotron isresistive, current applied to the lines 24 or 28 is redirected to theother cryotron which remains superconductive. This feature permits logiccryotrons to be selectively added or removed from the logic circuit byapplying or removing control current to the control cryotrons.

Prior to operation, the circuit of FIG. 1 is placed in a normalcondition where any current on the lines 24 and 28 will be bypassedaround all logic cryotrons and through the control cryotrons. This isaccomplished by first disconnecting the source 44 and 49 from the lines24 and 28 respectively, and sequentially connecting the switch arms 62,63, 66 and 67 to the contacts associated therewith. When a switch armengages a contact, current is supplied from the source to drive thecontrol cryotron resistive. Current in either the control cryotron orthe logic cryotron will be prevented from circulating therebetween.After sources 64 and 70 are disconnected from all lines 35', currentapplied to the lines 24 and 28 from the sources 44 and 49, respectivelywill bypass the logic cyrotron for reasons previously established.

The universal logic circuit is arranged for AND operation by firstplacing the circuit in the normal condition and thereafter applyingcontrol currents to the control cryotrons 22', 32', 40' and 52' whichbecome resistive causing the current from the sources 44 and 49 to flowto the logic cryotrons associated therewith, the latter cryotrons beingin a superconductive condition. The control currents to the controlcryotrons are supplied by the sources 64 and 70 and maintained duringthe entire AND operation. Accordingly, the logic block will now appearelectrically as that shown in FIG. 2. Thereafter, the currents to thelines 24 and 28 are disconnected and applied in accordance with thegiven input signal.

The AND operation of the circuit is indicated in the tabulation shown inFIG. 2a Assuming that signals are supplied by the sources 39 and 44 tothe lines 38 and 24 respectively, it will be seen that the cryotrons 22and 40 are driven resistive and current flows to the node 58 to indicatea binary 0 output. No current appears at the node 56 since the cryotrons22 and 40 are resistive and prevent current flow on the paths 26 and 28respectively. When the sources 44 and 43 are connected to the lines 24and 41, it will be seen that the cryotrons 32 and 52 are drivenresistive. Thus, again current appears at the node 58 but no currentappears at the node 56 for reasons previously explained.

When signal sources 39 and 49 are connected to the lines 38 and 28respectively, the cryotrons 22 and 40 are driven resistive which causescurrent to flow from the source 49 to the node 58 as in the previouscase. Current appears at the node 56 when the signal sources 43 and 49are connected to the lines 41 and 28, respectively. The cryotrons 32 and52 are driven resistive by the current on the line 41 which enablescurrent to flow from the source 49 to the node 56 to indicate abinary 1. Thus, the output from thecircuit of FIG. 2 is identical tothat of the conventional AND circuits. I

To change the circuit of FIG, 2 to an OR circuit as shown in FIG. 3, thecircuit is reset to the normal condition in the manner previouslydescribed. Thereafter, control current is applied to the controlcryotrons 22', 30' 42' and 52 which become resistive and enable currentfrom either the source 44 or 49 to flow through the logic cryotrons 22,30, 42 and 52 respectively. The logic circuit now appears electricallyas that shown in grasses FIG. 3. The tabulation shown in FIG. 3aindicates the operation of the circuit for the various signals suppliedto the leads 24, 28, 3S and 41 and corresponds to the well known ORcircuit. The operation of the circuit described by FIG. 3a is si nilarto that described for FIG. 2 and will be omitted for reasons of brevity.

The circuit of FIG. 1 is converted to an Exclusive OR function as shownin FIG. 4 by resetting the circuit to the normal condition andthereafter driving the control cryotrons 22', 3t), 42' and 59 resistiveas previously explained. Subsequently, the logic cryotrons 22, 3d, 42and 58 become superconductive to permit the desired logic operation. Thetabulation shown in EEG. 4a indicates the operation of the circuit forExclusive OR operation.

It should be noted in connection with FIGS. 1 through 4 that a pluralityof pairs of logic cryotrons control the flow of current on the lines 24and 28 to the nodes 5'3 and 56 respectively. Specifically, the cryotrons2t} and 22 and the cryotrons 3i and 32 are the pairs that control thecurrent on the line 24 to the node 5%. Similarly, the cryotrons 4-9 and42. and the cryotrons St? and 52 are the pairs which control the currenton the line 28 to the node 56. Conveniently, one of the logic cryotr-onsis shunted or bypassed to enable a particular logic operation to beperformed. Thus, for the AND function, the cryotrons 20 and 3% in thepairs associated with the lead 24 are bypassed and the cryotrons 42 and4d of the pairs associated with the lead 5e are bypassedv Similarly, foreach other logic operation, one unique cryotron in each pair associatedwith a conductive path is bypassed to adapt the circuit for theparticular logic operation. Since there are four pairs of logiccryotrons, and each pair is capable of two different conditions, a totalof 16 different logic functions may be obtained from the uni versalcircuit of the present invention. Furthermore, the symmetry of the logiccircuit simplifies the control circuit therefor which reduces the costand facilitates the operation thereof.

The logic circuit of FIG. 1 may be modified to combine logically morethan two independent variable. Referring to FIG. 5, a three variableuniversal logic block is shown assembled on a supporting member. Thethree variable logic circuits (x, y, z) comprise a pair of two variableuniversal logic circuits of the type shown in FIG. 1 and additionallogic circuitry for the third variable which selects one of the twovariable circuits. For reasons of convenience, like elements to thoseshown in FIG. 1 will have like reference designations, the twotwovariable logic circuits employed in PEG. 5 being distinguished from eachother by the subscripts a and (b-I Cryotrons 86, 82, 84, S6, 88, 9t 2and 94 included in the supporting member are responsive to a thirdbinary input sigal (z) to select one of the two-two variable logicblocks. The cryotrons 84, 8d, 92 and 9d are responsive to the input ofthe third variable whereas the cryo trons 8t), 82, 88 and 90 areresponsive to the 1 input of the third variable. To permit the 1 inputsignal to select between the two-two variable logic blocks, thecryotrons 32 and 83 and 86 and 92 have their gate conductors in the 1line of the input. The control leads of the former and the latter pairs,however, are in the l and "0 input lines, respectively, of the thirdvariable. Similarly, to permit the 0 input variable to select betweenthe two-two variable logic blocks, the cryotrons 38 and 9% and 84 and 94have their gate conductors in the 0 input line. The control leads of theformer and the latter pairs however, are in the l and 0 lines,respectively, of the third variable.

The circuit of FIG. operates as an AND circuit when the logic cryotronsa and I), 3th: and b, 42/1. and b, and 52a and 5% included therein arebypassed by the control cryotrons associated therewith. The procedurefor bypassing the logic cryotrons is the same as that 6 previouslydescribed in connection with the AND circuit of FIG. 2. The tabulationshown in FIG. 5a and labeled AND escribes the outputs from the circuitfor the various combination of input signals. Similarly, the tabulationsshown in FiGS. 51 and c and labelled OR and Exclusive OR respectively,describe the outputs from the circuit for the various combination ofinput signals supplied to the circuit.

In the case of the OR circuit logic cryotrons 26a, 22b, 32a and b, 459aand b, and 58a and b are bypassed, whereas the Exclusive OR functionshown in FIG. 5c is implemented by bypassing the same cryotrons, withthe single change that 5212 is bypassed instead of 5%. It will be notedthat the cryotrons selected in the a twotwo variable logic circuitprovide the output for the first four rows of the truth tables shown inFIGS. 5a, b and 0 whereas the cryotrons selected in the b twotwovariable logic circuit provide the output for the last four rows of thetruth tables shown in FIGS. 5a, b and c.

Specific operation of each logic circuit is the same as the describedfor FIGS. 2, 3 and 4 except that the third variable directs the inputsignal to a selected two variable circuit to obtain the desired output.A brief description will now follow.

Assume for example that the circuit of FIGURE 5 is arranged for ANDoperation. As previously describe the cryotrons 22a, 22b, 32a, 32b, 43a,b, a and 52b appear in their respective superconductive paths.Additionally, the cryotrons 3t}, 82, 34-, 85, 88, 90, 92, and 94 appearin their respective superconductive paths. The remaining cryotronsindicated in FTGURE 5 are shunted by their associated control cryotrons.Current sources M and 7% (see FIGURE 1) are operated to select thenecessary cryotrons to perform the desired logic operation. The currentsources 64 and 7% correspond to the X and Y inputs to the circuit ofFIGURE 5. The X and Y inputs function as first and second independentvariables supplied to the circuit. A third variable to the circuit isrepresented by a Z input. The Z input selects the circuit output asbetween the first and second varaibles.

FIGURE 5a discloses a truth table for the AND operation of the circuitshown in FIGURE 5. An output signal from the circuit is indicated atnode as or 58 for various combinations of input signals appearing onlines 24, 23, ml 102, 38 and 41. Assume for example, that the binaryinputs supplied to the circuit are those appearing on line 4 of thetruth table. The output at node 5'6, as a result, is a binary O. Thebinary 1, 0 and 1 inputs for Y, Z and X variables, respectively, renderthe cyrotrons 85, Ella and 32a resistive. Accordingly, the signalappearing on the line 28 flows through cryotrons 82 and shuntedcryotrons 42a, 52 and 9b to the node 58 to indicate a binary ll.Similarly, all other combinations of signal inputs to the circuit,except the last input, provide binary 0 outputs. The last inputindicated in FIG- URE 50, provides a binary 1 output. The binary 1, land 1 inputs for Y, Z and X variables, respectively, render cryotrons82a and 52b resistive. The signal appearing on line 23, as a result,flows through cryotrons 86, dill) and shuntted cryotron Sllb to the nodeS6 where a binary 1 output is provided.

Summarizing, briefly, the cryotrons through 94 select between the a andb sections of the circuit of FIG- URE 5 to provide an output. Theselecting cryotrons are always in the circuit and are not bypassed as inthe case of the cryotrons in the a andb section. Each section of thecircuit may be considered as logically combining two independent binaryvalues. Symbolically each section may be referred to as a K variable.Similarly, the selecting cryotrons employ another independent binaryvalue as a K-l- 1 variable to select between the K variables.

Although the present invention has shown a two and three variableuiversal logic block, it is believed apparent that the circuit can beextended to handle any number 2 of independent variables by employingcyrotrons corresponding to the cryotrons 80 through 94 as a (K +1)variable to select one of two K variable circuits.

Besides cryogenic systems. the present invention has equal applicationto other switching devices for example, photocells of the type disclosedin US. Patent 2,952,792 cited above. Control points in such anembodiment could be shuntted or bypassed by turning on the lightsupplied to the point, the light driving the control point to a lowresistance condition as explained in the cited Patent 2,952,792. Theremaining cells perform the selected logic function as the light isturned on or off according to one of the input variables, the otherinput variable being supplied to the conductive paths typically printedcircuit strips secured to the supporting member.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of this invention.

What is claimed is:

1. A universal logic circuit comprising at least two sets of conductivepaths, each conductive path of a set being connected to the otherconductive path of the set through an associated interconductive path, aplurality of pairs of switching devices, one switching device in eachpair being connected to a selected one of the conductive paths in a pairand the other switching device in a set being connected to theassociated interconductive path of the selected conductive path, meansfor shunting one switching device in each pair of switching devices toarrange the circuit for a preselected logic operation, and means forsupplying binary signals to the other switching devices in at least twoof the switching pairs which perform the selected logic operation of thecircuit.

2. The universal logic circuit defined in claim 1 wherein the means forsupplying binary signals to the other switching device comprises a firstsignal source indicative of a binary connected to one of the conductivepaths in the set, and a second signal source indicative of a binary 1connected to the other conductive path of the set.

3. The logic circuit, as defined in claim 7, arranged to perform an ORlogic operation wherein the first, third, fourth and sixth switchingdevices are shunted.

4. The universal logic circuit, as defined in claim 7, arranged toperform an Exclusive-OR logic operation wherein the first, third, sixthand eighth switching devices are shunted.

5. A universal logic circuit for combining logically a plurality ofindependent binary variables designated K variables with one more binaryvariable designated the K+ 1 variable comprising a first set ofconductive paths, each conductive path of the set being connected to theother conductive path of the set through an associated interconductivepath, a second set of conductive paths, each conductive path of thesecond set being connected to the other conductive path of the secondset through an associated interconductive path, a plurality of pairs ofswitching devices associated with the first and second sets ofconductive paths, means for shunting selected switching devices in eachset of conductive paths to arrange the set of conductive paths for adesired logic function, each set of conductive paths and unshuntedswitching devices being adapted to combine logically binary signalscorresponding to the K variables switching maens associated with eachset of switching devices and conductive paths to respond to the binaryK+ 1 variable to select one of the sets of switching devices andconductive paths responsive to he K variables and provide an outputcorresponding to the logic function of the sets of conductive paths.

6. A universal logic circuit comprising at least two sets ofsuperconductive paths, each superconductive path of a set beingconnected to the other superconductive path of the set through anassociated interconnected superconductive path, a plurality of pairs ofcryotrons, one cryotron in each pair being connected to a selected oneof the superconductive paths in a set and the other cryotron in a setbeing connected to the associated interconnected superconductive path ofthe selected superconductive path, means including control cryotrons forshunting one cryotron in each pair of cryotrons to arrange the circuitfor a preselected logic operation, and means for supplying first andsecond binary input signals to the unshunted cryotrons which perform theselected logic operation of the circuit. 7

7. A universal logic circuit comprising at least two sets ofsuperconductive paths, each superconductive path of a set beingconnected to the other superconductive path of the set through anassociated interconnecting superconductive path, a plurality of pairs oflogic cryotrons, one logic cryotron in each pair connected in serieswith one of the superconductive paths in the set and the other logiccryotron in the pair being connected in series with the associatedinterconnected superconductive path of the selected superconductivepath, control cryotron means connected in parallel with the logiccryotron included in the superconductive paths and the associatedinterconnected superconductive paths, selection means for driving allcontrol cryotrons to a resistive condition, and means for supplyingbinary signals to those logic cryotrons connected in parallel with thecontrol cryotrons and not in a resistive state.

8. A universal logic circuit comprising a first conductive path havingan input and an output, a second conductive path having an input and anoutput, first and second series switching means included in the firstconductive path, third and fourth series switching means included in thesecond conductive path, a first interconnecting conductive pathconnecting the input of the first conductive path to the output of thesecond conductive path, a second interconnecting conductive pathconnecting the input of the second conductive path to the output of thefirst conductive path, fifth and sixth series switching means includedin the first interconnecting conductive path, seventh and eighth seriesswitching means included in the second interconnecting conductive path,a first source of binary signals of one value connected to the first,third, fifth and seventh switching devices, a second source of binarysignals of a second value connected to the remaining switching devices,a third source of binary signals of value corresponding to the firstsource connected to the input of the first conductive path and a fourthsource of binary signals of value corresponding to the second sourceconnected to the input of the second conductive path, and means forshunting all switching devices to arrange for a desired logic operation.

9. The logic circuit, as defined in claim 8, arranged to perform an ANDoperation wherein the first, second, fourth and seventh cryotrons areshunted.

10. First and second universal logic circuits, as defined in claim 8,and switching means responsive to fifth and sixth binary signal valuescorresponding to the first and second binary sources to select betweenthe first and second circuits to provide an output which represents thelogic combination of the signals supplied to the circuit.

References Cited by the Examiner UNITED STATES PATENTS 3,004,705 10/61Bremer 307-88.5

ARTHUR GAUSS, Primary Examiner.

HERMAN KARL SAALBACH, Examiner.

1. A UNIVERSAL LOGIC CIRCUIT COMPRISING AT LEAST TWO SETS OF CONDUCTIVEPATHS, EACH CONDUCTIVE PATH OF A SET BEING CONNECTED TO THE OTHERCONDUCTIVE PATH OF THE SET THROUGH AN ASSOCIATED INTERCONDUCTIVE PATH, APLURALITY OF PAIRS OF SWITCHING DEVICES, ONE SWITCHING DEVICE IN EACHPAIR BEING CONNECTED TO A SELECTED ONE OF THE CONDUCTIVE PATHS IN A PAIRAND THE OTHER SWITHING DEVICE IN A SET BEING CONNECTED TO THE ASSOCIATEDINTERCONDUCTIVE PATH OF THE SELECTED CONDUCTIVE PATH, MEANS FOR SHUNTINGONE SWITCHING DEVICE IN EACH PAIR OF SWITCHING DEVICES TO ARRANGE THECIRCUIT FOR A PRESELECTED LOGIC OPERATION, AND MEANS FOR SUPPLYINGBINARY SIGNALS TO THE OTHER SWITCHING DEVICES IN AT LEAST TWO OF THESWITCHING PAIRS WHICH PERFORM THE SELECTED LOGIC OPERATION O F THECIRCUIT.